In the semiconductor industry the packaging of microelectronic components conventionally involves placement of electronic devices, or dies, on lead frames prior to encapsulation in protective package material. Lead frames are typically formed in arrays on metal strips or plates. A stamping process creates a matrix of lead frames, each including a die attachment site and package conductors, commonly package leads, to effect electrical communication with, for example, other components on a printed wiring board (PWB). A die is attached to each attachment site with an adhesive or soldering process. Wire bonding is then used to form electrical connections from the active die pads of each die to the package conductors. Plastic is injection-molded around the die and lead frame to form the typical black plastic body.
In the case of mounting more expensive or elaborate die, lead frame strips are constructed by perforating metal sheets typically ranging between 1.5 and 3.0 inches in width. These strips are 6 to 10 inches long and a few mils in thickness. Lead frame materials include copper or copper alloys, a copper core plated with nickel, and a copper core covered with flash gold, palladium, or silver. Lead frame strips may contain arrays of up to 100 or more mounting sites.
Demands for increasing the density of circuit functions on printed wiring boards are resulting in smaller and thinner integrated circuit packages. This is especially true for lead-frame devices having a low number of leads, e.g., 10 or fewer. Small profiles, such as available in the format of Quad-Flat Non-leaded (QFN) packaged devices, provide very short connection distances between the die and the lead frame conductors to achieve optimal electrical and thermal performance. These are suitable for performance up to 12 GHz, including applications in analog, RF, and mixed signal circuitry. They are often placed in wireless or handheld electronic systems such as phones, digital cameras and PDA's, where size and weight are important performance factors.
With this trend toward a near Chip Size Package (CSP), packages with 1 mm by 2 mm dimensions or less are now common, and the progression is toward even smaller sizes. Cost-effective volume production of these micro-packaged products is large, often on the order of a million parts or more per day at a single manufacturing facility. Consequently there is continued need to address cost, yield and throughput issues as device sizes continue to shrink. By testing devices in parallel and at greater rates, throughput can be optimized. With larger package sizes, this has been effected with Test Before Singulation (TBS) processes, i.e., testing of devices prior to singulation from the lead frame strip, at speeds on the order of 0.3 second per device. However, it becomes problematic to implement TBS processes as the dimensions of CSP packages become smaller. Special features must be incorporated to accommodate conventional TBS processes, e.g., sawing or etching, and to avoid damage to the devices.
When testing is performed after singulation, throughput test speeds can be less than one second per device. However, with the package leads having minimal contact dimensions, e.g., on the order of 0.15 mm, parts that are singulated and then socket tested may have lower first-pass yields than devices tested before singulation. This is attributable, in part, to alignment and orientation errors occurring in vision-based handling systems. For example, when systems place singulated parts in sockets, if the electrical contacts are not correct, then good parts are identified as failed.
It is preferred to have TBS processes which enable testing of more CSP devices in parallel and at higher rates than achievable when testing is performed after singulation. Even with specially designed lead frames and lead-isolation tooling, application of TBS processes to the smallest dimension CSP devices has been fraught with issues relating to cost, quality and alignment. It is a desire in the art to overcome these limitations because a TBS process could be used to further increase test throughput of CSP devices, e.g., by simultaneous test of multiple dies positioned in an array on a lead frame microstrip.